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EtronTech
Features
* Single power supply voltage of 2.3V to 3.6V * Power down features using CE# * Low power dissipation * Data retention supply voltage: 1.0V to 3.6V * Direct TTL compatibility for all input and output * Wide operating temperature range: -40C to 85C * Standby current @ VDD = 3.6 V
IDDS2 Typical EM564166BC-70/85 EM564166BC-70E/85E 1 A 5 A Maximum 10 A 80 A
D GND DQ11 A17 A7
EM564166
256K x 16 Low Power SRAM
Preliminary, Rev 1.0 Pin Configuration
48-Ball BGA (CSP), Top View
1 2 3 4 5 6
05/2001
A
LB#
OE#
A0
A1
A2
NC
B
DQ8
UB#
A3
A4
CE#
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
DQ3
VDD
E
VDD
DQ12
NC
A16
DQ4
GND
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
NC
A12
A13
WE#
DQ7
Ordering Information
Part Number
EM564166BC-70 EM564166BC-85 EM564166BC-70E EM564166BC-85E
H
NC
A8
A9
A10
A11
NC
Speed
70 ns 85 ns 70 ns 85 ns
IDDS2
10 A 10 A 80 A 80 A
Package
6x8 BGA 6x8 BGA 6x8 BGA 6x8 BGA
Pin Description
Symbol
A0 - A17 DQ0 - DQ15 CE# OE# WE# LB#, UB# GND VDD NC
Function
Address Inputs Data Inputs / Outputs Chip Enable Inputs Output Enable Read / Write Control Input Data Byte Control Inputs Ground Power Supply No Connection
Overview
The EM564166 is a 4,194,304-bit SRAM organized as 262,144 words by 16 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.3V to 3.6V power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE#) is asserted high. There are two control inputs. CE# are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from 40C to 85C, the EM564166 can be used in environments exhibiting extreme temperature conditions.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
Block Diagram
EM564166
A0 MEMORY CELL ARRAY 2,048X128X16 (4,194,304) A17
VDD
GND
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
SENSE AMP
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 COLUMN ADDRESS DECODER
WE# UB#
LB#
OE# CE#
POWER DOWN CIRCUIT
Preliminary
2
Rev 1.0
May 2001
EtronTech
Operating Mode
Mode CE# OE# WE# LB# L Read L L H H L L Write L X L H L L Output Deselect L H Standby X X X X X X X X X H X H X High-Z High-Z H H X UB# L L H L L H X High-Z High-Z DQ0~DQ7 DOUT High-Z DOUT DIN High-Z DIN DQ8~DQ15 DOUT DOUT High-Z DIN DIN High-Z
EM564166
Note: X = don't care. H=logic high. L=logic low. Absolute Maximum Ratings
Supply voltage, VDD Input voltages, VIN Input and output voltages, VI/O Operating temperature, TOPR Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD -0.3 to +4.6V -0.3 to +4.6V -0.5 to VDD +0.5V -40 to +85C -55 to +150C 240C 0.6 W
DC Recommended Operating Conditions (Ta=-40C to 85C)
Symbol VDD VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 2.3 2.2 -0.3
(2)
Typ - - - -
Max 3.6 VDD + 0.3 0.6 3.6
(1)
Unit V V V V
VDR Data Retention Supply Voltage Note: (1) Overshoot : VDD +2.0V in case of pulse width 20ns (2) Undershoot : -2.0V in case of pulse width 20ns
1.0
Preliminary
3
Rev 1.0
May 2001
EtronTech
DC Characteristics (Ta = -40C to 85C, VDD = 2.3V to 3.6V)
Parameter Input low current Output low voltage Output high voltage Symbol IIL VOL VOH IIN = 0V to VDD IOL = 2.1 mA IOH = -1.0 mA VDD = 3.6 V IDD1 Operating current CE# = VIL and IOUT = 0mA Other Input = VIH / VIL IDD2 IDDS1 Standby current IDDS2 CE# = VIH CE# VDD - 0.2V VDD = 3.6 V -70/85 VDD = 2.7 V VDD = 2.3 V VDD = 3.6 V Cycle time = min VDD = 2.7 V VDD = 2.3 V Cycle time = 1s Test Conditions Min -1 VDD 0.15 - - - - - - - - -
EM564166
Typ* - - - 15 10 7 - - 1 0.8 0.5 5
Max Unit 1 0.4 - 25 15 mA 12 5 0.5 10 5 3 80 A mA A V V
-70E/85E Notes: * Typical value are measured at Ta = 25C.
Capacitance (Ta = 25C; f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol CIN Min - Typ - Max 10 Unit pF Test Conditions VIN = GND
COUT 10 pF VOUT = GND - - Notes: This parameter is periodically sampled and is not 100% tested.
Preliminary
4
Rev 1.0
May 2001
EtronTech
Read Cycle
EM564166
AC Characteristics and Operating Conditions (Ta = -40C to 85C, VDD = 2.3V to 3.6V)
EM564166 Symbol tRC tAA tCO1 tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH Write Cycle EM564166 Symbol tWC tWP tCW tBW tAS tWR tWHZ tOW tDS tDH Write cycle time Write pulse width Chip Enable to end of write Data Byte Control to end of Write Address setup time Write Recovery time WE# Low to Output in High-Z WE# High to Output in Low-Z Data Setup Time Data Hold Time Parameter -85 -70 Unit - - - - - - 30 - - - ns Min Max Min Max 85 55 70 70 0 0 - 5 35 0 - - - - - - 35 - - - 70 55 60 60 0 0 - 5 30 0 Read cycle time Address access time Chip Enable (CE#) Access Time Output enable access time Data Byte Control Access Time Chip Enable Low to Output in Low-Z Output enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Parameter -85 -70 Unit - 70 70 35 35 - - - 25 25 25 - ns Min Max Min Max 85 - - - - 10 3 5 - - - 10 - 85 85 45 45 - - - 35 35 35 - 70 - - - - 10 3 5 - - - 10
AC Test Condition
* Output load : 50pF + one TTL gate * Input pulse level : 0.4V, 2.4V * Timing measurements : 0.5 x VDD * tR, tF : 5ns
Preliminary
5
Rev 1.0
May 2001
EtronTech
Read Cycle (See Note 1)
t RC
EM564166
Ad d r e ss
t AA
t OH
t CO1
C E#
t HZ
t OE
O E#
t OHZ
t BA
U B# , L B# t BLZ t OLZ t LZ t BHZ
DO U T
VALID DATA OUT
Preliminary
6
Rev 1.0
May 2001
EtronTech
Write Cycle1 (WE# Controlled)(See Note 4)
tW C
EM564166
Address
t AS
tW P
tW R
W E#
t CW
CE#
t BW
UB# , LB# t W HZ t OW
D O UT
(See Note2)
(See Note3)
t DS
t DH
D IN
(See Note 5)
VALID DATA IN
(See Note 5)
Preliminary
7
Rev 1.0
May 2001
EtronTech
Write Cycle 2 (CE# Controlled)(See Note 4)
tW C
EM564166
Address
t AS
tW P
tW R
W E#
t CW
CE#
t BW
UB# , LB# t BLZ t W HZ
D O UT t LZ t DS t DH
D IN
(See Note 5)
VALID DATA IN
Preliminary
8
Rev 1.0
May 2001
EtronTech
Write Cycle3 (UB#, LB# Controlled)(See Note 4)
tW C
EM564166
Address
t AS
tW P
tW R
W E#
t CW
CE#
t BW
UB# , LB# t BLZ t W HZ
D O UT t LZ t DS t DH
D IN
(See Note 5)
VALID DATA IN
Note:
1. 2. 3. 4. 5. WE# remains HIGH for the read cycle. If CE# goes LOW with or after WE# goes LOW, the outputs will remain at high impedance. If CE# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
Preliminary
9
Rev 1.0
May 2001
EtronTech
Data Retention Characteristics (Ta = -40C to 85C)
Symbol Data Retention Supply Voltage Data Retention Current Parameter CE# VDD - 0.2V, VIN VDD - 0.2V or VIN 0.2V VDD = 1.0V, CE# VDD - 0.2V, VIN VDD - 0.2V or VIN 0.2V Min
EM564166
Typ
Max
Unit
VDR IDR tSDR tRDR
1.0 - 0 tRC
- 0.5 - -
3.6 3.5 - -
V A ns ns
Chip Deselect to Data Retention Mode Time Recovery Time
CE# Controlled Data Retention Mode
t SDR V DD 2.7V Data Retention Mode t RDR
2.2V V DR CE# GND Note 1
Note:
1. CE# VDD - 0.2V or UB# = LB# VDD - 0.2V
Preliminary
10
Rev 1.0
May 2001
EtronTech
Package Diagrams 48-Ball (6mm x 8mm) BGA Units in mm
TOP VIEW
EM564166
BOTTOM VIEW 0.10 S 0.25 S C C
PIN 1 CORNER
A
B
PIN 1 CORNER
0.30 3 4 5 6 6 5 4 3
0.05(48X) 2 1
1
2
-B0.75 3.75 -A0.20(4X)
0.10 -CSEATING PLANE
Preliminary
11
Rev 1.0
May 2001

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